The desired speed (i.e., bit rate) of broadband serial data communication systems is constantly increasing. Although semiconductor process improvements are enabling the design of processing circuitry that supports these higher speeds, challenging problems are emerging related to the reliable capture of data at the receiver side of these communication systems. For example, due to the decreasing geometries of semiconductor processes, the available voltage for signaling and for supplying analog circuits is decreasing. This is degrading the signaling signal-to-noise (S/N) ratio while complicating the design of high-speed receiver circuits due to limited voltage headroom. Also, because physical transmission paths in many of these communications systems are not being significantly improved, received signals are suffering more and more from parasitic dispersive and reflective effects of the transmission paths. Addressing this often requires adaptive equalization which increases the need for precision control over the gain, range, offset, and linearity of the high-speed receiver circuits. Furthermore, the use of multiple level pulse amplitude modulation (multi-PAM) signaling is becoming more common to reduce the signaling problems mentioned above. However, the smaller voltage levels used in multi-PAM systems also drives the need for precision control over the gain, range, offset, and linearity of the high-speed receiver circuits.
Several topologies have been used for receiver circuits to enable the reception of high-speed, small-amplitude, multi-PAM signals. For example, controllable input offset voltage has sometimes been enabled within samplers of the high-speed receiver circuits to enable sampling at the centers of least significant bit (LSB) eyes. Also, preamplifiers have sometimes been used in front of the samplers. However, these and other circuit techniques suffer from some or all of the following problems: 1.) gain compression leading to reduced S/N ratio; 2.) sampler kickback affecting the sampling resolution, and therefore the effective S/N ratio; 3.) non-linear input offset voltage control as a function of input signal common mode level; 4.) lack of control over systematic integral non-linearity (INL) of the input offset voltage control transfer function; 5.) de-coupling of offset between preamplifiers and samplers which complicates offset cancellation and sampler swapping; and 6.) non-linear input offset voltage control transfer functions.
To demonstrate some of the above-mentioned problems, assume a high-speed communication system that supports differential signaling. Differential signaling typically requires differential receiver circuits having differential amplifier circuitry. Also, it is desirable to implement differential amplifier circuitry with a controllable input offset voltage. Such differential amplifier circuitry requires a differential voltage applied at its inputs equal and opposite to the input offset voltage to produce a zero differential voltage at its outputs. As used herein the term “twist voltage” refers to the differential input voltage required at the input of a differential amplifier in order to obtain a zero (or substantially zero) differential output voltage. It is desirable to implement differential amplifier circuitry where the value of the twist voltage is controllable, preferably through a substantially linear transfer function. An example application for such differential amplifier circuitry is in a differential 4-level pulse amplitude modulation (4-PAM) signal receiver, where differential amplifiers, with controllable input offset voltage, could serve as preamplifiers for feeding LSB samplers. This enables samplers with zero differential voltage thresholds to be effectively used for sampling at the centers of LSB eyes. By adjusting the twist voltage of the pre-amplifiers, the effective sampling level could be adjusted depending on the magnitude of the 4-PAM signal present at the receiver, since this magnitude affects the centers of the LSB eyes.
Before describing the details of a differential amplifier with substantially linear twist voltage control for use with differential 4-PAM signals, it is useful to first describe the details of 4-PAM signaling. Thus, referring to FIG. 1, signal waveforms for a single-ended 4-PAM signaling system are shown, along with reference levels (i.e., VrefH, VrefM, and VrefL), logic signal levels (i.e., in Gray code sequence 0, 1, 3, and 2), and logic signal level binary values (i.e., in Gray code sequence 00, 01, 11, and 10). The reference levels are used to determine most significant bits (MSBs) and least significant bits (LSBs) of signals in terms of the logic signal level binary values. That is, the MSB of a signal may be extracted by a simple comparison of the signal to the VrefM reference level. In contrast, the LSB of a signal must be extracted through a simultaneous comparison of the signal to both the VrefH and VrefL reference levels.
Single-ended multi-level signaling systems, such as the single-ended 4-PAM signaling system discussed above, are often implemented to alleviate signal attenuation problems which are frequently encountered in high-speed (e.g., above 5 Gb/s) serial link channels, which are often found in backplane environments. However, despite the benefits obtained through the use of single-ended multi-level signaling systems, further solutions may also be required to address such signal attenuation problems. One such solution is realized through the use of differential multi-level signaling systems due primarily to the benefits that differential signaling offers in the area of common-mode noise rejection.
Referring to FIG. 2, a differential signal waveform (i.e., Vin(diff)=Vin(+)−Vin(−)) for a differential 4-PAM signaling system is shown, along with reference twist voltage levels (i.e., VrefH, VrefM, and VrefL), differential logic signal level binary values (i.e., in Gray code sequence 00, 01, 11, and 10), Vin(diff) logic signal levels (i.e., in Gray code sequence 0, 1, 3, and 2), and Vin(diff) MSB & LSB logic value ranges. Analogous to the case for the single-ended 4-PAM signaling system described above, the reference levels are used to determine MSBs and LSBs of the differential signal in terms of the differential logic signal level binary values. That is, the MSB of the differential signal may be extracted by a simple differential comparison of the differential signal to the VrefM reference level. In contrast, the LSB of the differential signal must be extracted through a simultaneous comparison of the differential signal to both the VrefH and VrefL reference levels.
With the details of 4-PAM signaling having been described, the details of a differential amplifier with substantially linear twist voltage control for use with differential 4-PAM signals may now be described. Thus, one way to implement a differential amplifier with substantially linear twist voltage control for use with differential 4-PAM signals is to use two oppositely skewed differential pairs to drive a shared differential load. For example, referring to FIG. 3, there is shown a differential amplifier 100 comprising a first differential transistor pair 102, a second differential transistor pair 104, a first current source 106, a second current source 108, a first load 110 (i.e., resistance R), and a second load 112 (i.e., resistance R), wherein M represents a normalized size of the transistors in the first 102 and second 104 differential transistor pairs, N represents a transistor size ratio variable, and α represents a current steering variable. By steering a fixed amount of tail current, It, from the first differential transistor pair 102 to the second differential transistor pair 104, or vice versa, the effective twist voltage can be adjusted from +Vtwistmax to −Vtwistmax, where Vtwistmax is the systematic offset voltage of each of the first differential transistor pair 102 and the second differential transistor pair 104, as shown in FIG. 4, wherein Vin(diff) represents the differential signal formed of input signals Vin(+) and Vin(−) and Vout(diff) represents the differential signal formed of output signals Vout(+) and Vout(−). This systematic offset voltage is due to the difference in size between the two transistors in each of the first differential transistor pair 102 and the second differential transistor pair 104. The magnitude of the systematic offset voltage for each differential transistor pair is approximately proportional to the square root of its tail current, It, and the square root of its transistor size ratio.
If all of the components in the differential amplifier 100 match perfectly, the resulting current steering to twist voltage transfer function will look similar to the solid curve shown in FIG. 5. Note that although the solid curve shown in FIG. 5 is symmetrical about the origin, it is slightly non-linear. At any value of current steering (α), the integral non-linearity (INL) of the transfer function is the difference between the solid curve and the dotted, perfectly linear curve.
The INL shown in FIG. 5 is moderate in magnitude and is systemic. Therefore, many applications would find this INL to be either acceptable as is or easy to compensate for using any of several circuit techniques. However, device mismatches in actual circuit implementations may both randomly shift and randomly rotate the transfer function curve of FIG. 5, effectively changing and unbalancing both the y-axis crossing point (nominal twist voltage) and the y-axis endpoints (twist voltage range) of the transfer function curve, such as shown in FIG. 6. Both of these effects can not only worsen the absolute INL of each amplifier, but they can also severely worsen the relative INL's between amplifiers. They can further cause the twist voltage range to either be too small or too big. These issues may be unacceptable, particularly in circuits where matching twist voltages between two or more amplifiers is important.
In view of the foregoing, it would be desirable to provide a technique for reducing the effects of random mismatches in circuit components of differential amplifiers which overcomes the above-described inadequacies and shortcomings.